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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
FEATURES
* 18 LVCMOS outputs, 23 typical output impedance * Output frequency up to 200MHz * 150ps output skew * Part to part skew: 850ps * Selectable LVCMOS or differential clock input * LVTTL / LVCMOS clock select input * Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS83940 is a low skew, 1-to-18 Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 18 to 36 by utilizing the ability of the outputs to drive two series terminated lines. The differential clock input is designed to accept any differential input levels including LVPECL.
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The ICS83940 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83940 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
VDDO GND Q0 Q1 Q2 Q3 Q4 Q5
CLK_SEL CLK0 nCLK0 LVCMOS_CLK GND Q0
1
32 31 30 29 28 27 26 25
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q17 Q16 Q15 GND Q14 Q13 Q12 VDDO
24 23 22
Q6 Q7 Q8 VDDI Q9 Q10 Q11 GND
GND LVCMOS_CLK
Q1 - Q16
CLK_SEL CLK nCLK
ICS83940
21 20 19 18 17
Q17
VDDI VDDO
32-Lead LQFP Y Pacakge 7mm x 7mm x 1.4mm package body Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83940AY
www.icst.com/products/hiperclocks.html 1
REV. B JULY 31, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
Name GND Type Power Input Input Input Input Power Power Output Description Output power supply ground. Connect to ground.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 12, 17, 25 3 4 5 6 7, 21 8, 16, 29 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32
LVCMOS_CLK CLK_SEL CLK nCLK VDDI VDDO Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0
Pulldown Clock input. LVCMOS interface levels. Clock select input. Select LVCMOS clock input Pulldown when HIGH. Selects LVPECL clock inputs when LOW. Non-inver ting differential clock input. Any differential Pulldown inteface levels. Inver ting differential clock input. Any differential Pullup inteface levels. Input power supply. Connect to 3.3V or 2.5V. Output power supply. Connect to 3.3V or 2.5V. Clock outputs. 23 typical output impedance. LVCMOS interface levels
TABLE 2. PIN CHARACTERISTICS
Symbol CIN Parameter Input Capacitance CLK0, nCLK0, LVCMOS_CLK CLK_SEL VDDI, VDDO = 3.465V CPD Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance VDDI = 3.465V, VDDO = 2.625V VDDI, VDDO = 2.625V RPULLUP RPULLDOWN ROUT 51 51 23 Test Conditions Minimum Typical Maximum 4 4 Units pF pF pF pF pF K K
83940AY
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REV. B JULY 31, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
Clock CLK0, nCLK0 Selected De-selected LVCMOS_CLK De-selected Selected
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input CLK_SEL 0 1
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK-SEL 0 0 0 0 0 0 1 LVCMOS_CLK -- -- -- -- -- -- 0 CLK0 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 -- nCLK0 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 -- Outputs Q0 thru Q17 LOW HIGH LOW HIGH HIGH LOW LOW Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Single Ended to Single Ended Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting Non Inver ting
1 1 -- -- HIGH Single Ended to Single Ended Non Inver ting NOTE 1: Single ended input use requires that one of the differential inputs be biased. The voltage at the biased input sets the switch point for the single ended input. For LVCMOS input levels the recommended input bias network is a resistor to VDDI, a resistor of equal value to ground and a 0.1F capacitor from the input to ground. The resulting switch point is VDDI/2.
83940AY
www.icst.com/products/hiperclocks.html 3
REV. B JULY 31, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
4.6V -0.5V to VDD+0.5 V -0.5V to VDD+0.5V 46C/W (0lfpm) -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, Tstg
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. DC CHARACTERISTICS, VDDI = VDDO = 3.3V5%, TA = 0 TO 70
Symbol Parameter VDDI VDDO IDD Input Power Supply Voltage Output Power Supply Voltage Power Supply Current VDDI = VDDO = 3.465V Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 70 Units V V mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI = VDDO = 3.3V5%, TA = 0 TO 70
Symbol Parameter VIH VIL Input High Voltage Input Low Voltage REF_CLK CLK_SEL REF_CLK CLK_SEL REF_CLK, CLK_SEL REF_CLK, CLK_SEL Test Conditions VDDI = 3.465V VDDI = 3.135V VDDI = 3.135V VDDI = VIN = 3.465V VDDI = 3.465V, VIN = 0V VDDO = 3.135V, IOH = -20mA VDDO = 3.135V, IOL = 20mA -5 2.4 0.6 Minimum 2 -0.3 -0.3 Typical Maximum 3.8 1.3 0.8 150 Units V V V A A V V
IIH IIL VOH VOL
Input High Current Input Low Current Output High Voltage Output Low Voltage
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDDI = VDDO = 3.3V5%, TA = 0 TO 70
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK0 nCLK0 CLK0 nCLK0 Test Conditions VDDI = VIN = 3.465V VDDI = VIN = 3.465V VDDI = 3.465V, VIN = 0V VDDI = 3.465V, VIN = 0V -5 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Input Common Mode Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
83940AY
www.icst.com/products/hiperclocks.html 4
REV. B JULY 31, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
Test Conditions CLK, nCLK CLK, nCLK 0 < f 200MHz 0 < f 200MHz Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 20% to 80% @ 50MHz 20% to 80% @ 50MHz Minimum Typical 2.3 Maximum 200 4 Units MHz ns ns ps ps ns ns 55 %
TABLE 5A. AC CHARACTERISTICS, VDDI = VDDO = 3.3V5%, TA = 0 TO 70
Symbol fMAX tpLH tpHL tsk(o) tsk(pp) tR tF Parameter Maximum Input Frequency Propagation Delay; NOTE 1 Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time
150 850
odc Output Duty Cycle 45 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions, and using the same type of inputs. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY
www.icst.com/products/hiperclocks.html 5
REV. B JULY 31, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
Test Conditions Minimum 3.135 2.375 VDDI = 3.465V, VDDO = 2.625V Typical 3.3 2.5 Maximum 3.465 2.625 Units V V mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDDI = 3.3V5%; VDDO = 2.5V5%, TA = 0 TO 70
Symbol Parameter VDDI VDDO IDD Input Power Supply Voltage Output Power Supply Voltage Power Supply Current
TABLE 4E. LVCMOS DC CHARACTERISTICS, VDDI = 3.3V5%; VDDO = 2.5V5%, TA = 0 TO 70
Symbol Parameter VIH VIL Input High Voltage Input Low Voltage REF_CLK CLK_SEL REF_CLK CLK_SEL REF_CLK, CLK_SEL REF_CLK, CLK_SEL Test Conditions VDDI = 3.465V VDDI = 3.135V VDDI = VIN = 3.465V VDDI = 3.465V, VIN = 0V VDDO = 2.375V, IOH = -12mA VDDO = 2.375V, IOL = 12mA -5 1.8 0.5 Minimum 2 -0.3 Typical Maximum 3.8 1.3 150 Units V V A A V V
IIH IIL VOH VOL
Input High Current Input Low Current Output High Voltage Output Low Voltage
TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDDI = 3.3V5%; VDDO = 2.5V5%, TA = 0 TO 70
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK0 nCLK0 CLK0 nCLK0 Test Conditions VDDI = VIN = 3.465V VDDI = VIN = 3.465V VDDI = 3.465V, VIN = 0V VDDI = 3.465V, VIN = 0V -5 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Input Common Mode Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
83940AY
www.icst.com/products/hiperclocks.html 6
REV. B JULY 31, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
Test Conditions CLK, nCLK CLK, nCLK 0 < f 200MHz 0 < f 200MHz Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 20% to 80% @ 50MHz 20% to 80% @ 50MHz Minimum Typical Maximum Units MHz ns ns ps ps ns ns %
TABLE 5B. AC CHARACTERISTICS, VDDI = 3.3V5%, VDDO = 2.5V5%, TA = 0 TO 70
Symbol fMAX tpLH tpHL tsk(o) tsk(pp) tR tF Parameter Maximum Input Frequency Propagation Delay; NOTE 1 Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time
odc Output Duty Cycle All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions, and using the same type of inputs. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY
www.icst.com/products/hiperclocks.html 7
REV. B JULY 31, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
Test Conditions Minimum 2.375 2.375 VDDI = VDDO = 2.625V Typical 2.5 2.5 Maximum 2.625 2.625 Units V V mA
TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDDI = VDDO = 2.5V5%, TA = 0 TO 70
Symbol Parameter VDDI VDDO IDD Input Power Supply Voltage Output Power Supply Voltage Power Supply Current
TABLE 4H. LVCMOS DC CHARACTERISTICS, VDDI = VDDO = 2.5V5%, TA = 0 TO 70
Symbol Parameter VIH VIL Input High Voltage Input Low Voltage REF_CLK CLK_SEL REF_CLK CLK_SEL REF_CLK, CLK_SEL REF_CLK, CLK_SEL Test Conditions VDDI = 2.625V VDDI = 2.375V VDDI = VIN = 2.625V VDDI = 2.625V, VIN = 0V VDDO = 2.375V, IOH = -12mA VDDO = 2.375V, IOL = 12mA -5 1.8 0.5 Minimum 2 Typical Maximum 2.96 0.8 150 Units V V A A V V
IIH IIL VOH VOL
Input High Current Input Low Current Output High Voltage Output Low Voltage
TABLE 4I. DIFFERENTIAL DC CHARACTERISTICS, VDDI = VDDO = 25V5%, TA = 0 TO 70
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK0 nCLK0 CLK0 nCLK0 Test Conditions VDDI = VIN = 2.625V VDDI = VIN = 2.375V VDDI = 2.625V, VIN = 0V VDDI = 2.625V, VIN = 0V -5 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Input Common Mode Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
83940AY
www.icst.com/products/hiperclocks.html 8
REV. B JULY 31, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
Test Conditions CLK, nCLK CLK, nCLK 0 < f 200MHz 0 < f 200MHz Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 20% to 80% @ 50MHz 20% to 80% @ 50MHz Minimum Typical Maximum Units MHz ns ns ps ps ns ns %
TABLE 5C. AC CHARACTERISTICS, VDDI = VDDO = 2.5V5%, TA = 0 TO 70
Symbol fMAX tpLH tpHL tsk(o) tsk(pp) tR tF Parameter Maximum Input Frequency Propagation Delay; NOTE 1 Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time
odc Output Duty Cycle All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages, with equal load conditions, and using the same type of inputs. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY
www.icst.com/products/hiperclocks.html 9
REV. B JULY 31, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-026
83940AY
www.icst.com/products/hiperclocks.html 10
REV. B JULY 31, 2001
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS83940
LOW SKEW, 1-TO-18 LVCMOS FANOUT BUFFER
Marking ICS83940AY ICS83940AY Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS83940AY ICS83940AYT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83940AY
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REV. B JULY 31, 2001

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